1 ps8440c 07/24/01 pin description product features ? high performance phase-locked loop clock distribution for synchronous dram, server and networking applications. ? zero input-to-output delay: distribute one clock input to four banks of four outputs, with separate output enables for each bank. ? allow clock input to have spread spectrum modulation for emi reduction. the clock outputs track the clock input modulation. ? maximum clock frequency of 150 mhz. ? low jitter: cycle-to-cycle jitter 100ps max ? operates at 3.3v v cc ? available packaging: ? 48-pin tssop (thin shrink small outline) (a) description the pi6c2516 family is a low-skew, low jitter, phase-locked loop (pll) clock driver, distributing high-frequency clock signals for sdram, server and networking applications. by connecting the feedback fb_out output to the feedback fb_in input, the propa- gation delay from the clk input to any clock output will be nearly zero. this zero-delay feature allows the clk input clock to be distributed, providing 4 banks of four outputs. for test purposes, the pll can be bypassed by strapping the av cc to ground. the pi6c2516 family has the same pinout as the ti cdc2516, with the added feature of allowing spread spectrum clock input. block diagram clk fb_in av cc 4 4y [0:3] fb_out 4g pll 4 3y [0:3] 3g 4 2y [0:3] 2g 4 1y [0:3] 1g 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2516 phase-locked loop clock driver with 16 clock outputs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 v cc 1y0 1y1 gnd gnd 1y2 1y3 v cc 1g gnd av cc clk agnd agnd gnd 2g v cc 2y0 2y1 gnd gnd 2y2 2y3 v cc v cc 4y0 4y1 gnd gnd 4y2 4y3 v cc 4g gnd av cc fb_in agnd fb_out gnd 3g v cc 3y0 3y1 gnd gnd 3y2 3y3 v cc 48-pin a
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2516 phase-locked loop clock driver with 16 clock outputs 2 ps8440c 07/24/01 e m a n n i pr e b m u n n i pe p y tn o i t p i r c s e d k l c2 1i . m u r t c e p s d a e r p s s w o l l a k l c . t u p n i k c o l c n i _ b f7 3i . t u p n i k c a b d e e fn i _ b f. l l p l a n r e t n i e h t o t l a n g i s k c a b d e e f e h t s e d i v o r p k l c - d n an i _ b f - e s a h p o r e z y l l a m r o n s i e r e h t t a h t o s d e z i n o r h c n y s e r a d n a k l c n e e w t e b r o r r en i _ b f. g 19i o t d e l b a s i d e r a ] 3 : 0 [ y 1 s t u p t u o , w o l s i g 1 n e h w . e l b a n e k n a b t u p t u o d n a d e l b a n e e r a ] 3 : 0 [ y 1 s t u p t u o l l a , h g i h s i g 1 n e h w . e t a t s w o l c i g o l a . k l c s a y c n e u q e r f e m a s e h t t a d e h c t i w s g 26 1i o t d e l b a s i d e r a ] 3 : 0 [ y 2 s t u p t u o , w o l s i g 2 n e h w . e l b a n e k n a b t u p t u o d n a d e l b a n e e r a ] 3 : 0 [ y 2 s t u p t u o l l a , h g i h s i g 2 n e h w . e t a t s w o l c i g o l a . k l c s a y c n e u q e r f e m a s e h t t a d e h c t i w s g 33 3i o t d e l b a s i d e r a ] 3 : 0 [ y 3 s t u p t u o , w o l s i g 3 n e h w . e l b a n e k n a b t u p t u o d n a d e l b a n e e r a ] 3 : 0 [ y 3 s t u p t u o l l a , h g i h s i g 3 n e h w . e t a t s w o l c i g o l a . k l c s a y c n e u q e r f e m a s e h t t a d e h c t i w s g 40 4i o t d e l b a s i d e r a ] 3 : 0 [ y 4 s t u p t u o , w o l s i g 4 n e h w . e l b a n e k n a b t u p t u o d n a d e l b a n e e r a ] 3 : 0 [ y 4 s t u p t u o l l a , h g i h s i g 4 n e h w . e t a t s w o l c i g o l a . k l c s a y c n e u q e r f e m a s e h t t a d e h c t i w s t u o _ b f5 3o . t u p t u o k c a b d e e ft u o _ b f. k c a b d e e f l a n r e t x e r o f d e t a c i d e d s it u o _ b fn a s a h 5 2 d e d d e b m e w . s t u p t u o k c o l c e h t s a e u l a v e m a s e h t f o r o t s i s e r g n i p m a d - s e i r e s ] 3 : 0 [ y 17 , 6 , 3 , 2o . n i _ k l c f o s e i p o c w e k s - w o l e d i v o r p s t u p t u o e s e h t . s t u p t u o k c o l c 5 2 d e d d e b m e n a s a h t u p t u o h c a e w e h t f o r o t s i s e r g n i p m a d - s e i r e s . s t u p t u o k c o l c e h t s a e u l a v e m a s ] 3 : 0 [ y 23 2 , 2 2 , 9 1 , 8 1o . n i _ k l c f o s e i p o c w e k s - w o l e d i v o r p s t u p t u o e s e h t . s t u p t u o k c o l c 5 2 d e d d e b m e n a s a h t u p t u o h c a e w e h t f o r o t s i s e r g n i p m a d - s e i r e s . s t u p t u o k c o l c e h t s a e u l a v e m a s ] 3 : 0 [ y 31 3 , 0 3 , 7 2 , 6 2o . n i _ k l c f o s e i p o c w e k s - w o l e d i v o r p s t u p t u o e s e h t . s t u p t u o k c o l c 5 2 d e d d e b m e n a s a h t u p t u o h c a e w e h t f o r o t s i s e r g n i p m a d - s e i r e s . s t u p t u o k c o l c e h t s a e u l a v e m a s ] 3 : 0 [ y 47 4 , 6 4 , 3 4 , 2 4o . n i _ k l c f o s e i p o c w e k s - w o l e d i v o r p s t u p t u o e s e h t . s t u p t u o k c o l c 5 2 d e d d e b m e n a s a h t u p t u o h c a e w e h t f o r o t s i s e r g n i p m a d - s e i r e s . s t u p t u o k c o l c e h t s a e u l a v e m a s v a c c 8 3 , 1 1r e w o p v a . y l p p u s r e w o p g o l a n a c c r o f l l p e h t s s a p y b o t d e s u o s l a e b n a c v a n e h w . s e s o p r u p t s e t c c k l c d n a d e s s a p y b s i l l p , d n u o r g o t d e p p a r t s s i . s t u p t u o e c i v e d e h t o t y l t c e r i d d e r e f f u b s i d n g a6 3 , 4 1 , 3 1d n u o r g . y r t i u c r i c g o l a n a e h t r o f e c n e r e f e r d n u o r g e h t s e d i v o r p d n g a . d n u o r g g o l a n a v c c 8 4 , 1 4 , 2 3 , 5 2 , 4 2 , 7 1 , 8 , 1r e w o py l p p u s r e w o p d n g , 9 2 , 8 2 , 1 2 , 0 2 , 5 1 , 0 1 , 5 , 4 5 4 , 4 4 , 9 3 , 4 3 d n u o r gd n u o r g pin functions
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2516 phase-locked loop clock driver with 16 clock outputs 3 ps8440c 07/24/01 l o b m y sr e t e m a r a p. n i m. x a ms t i n u v c c e g n a r e g a t l o v y l p p u s5 . 0 ?6 . 4 v v i e g n a r e g a t l o v t u p n i ) 1 ( 5 . 0 ?5 . 6 v o t u p t u o y n a o t d e i l p p a e g n a r e g a t l o v ) 2 , 1 ( 5 . 0 ?v c c 5 . 0 + v k i t n e r r u c p m a l c t u p n i0 5 ? a m i o c d _v ( t n e r r u c t u p t u o s u o u n i t n o c o v r o 0 = c c )0 5 i o c d _v h g u o r h t t u p t u o s u o u n i t n o c c c d n u o r g r o0 0 1 r e w o pt t a n o i t a p i s s i d r e w o p m u m i x a m a 5 5 = o r i a l l i t s n i c ) 3 ( 5 8 . 0w t g t s e r u t a r e p m e t e g a r o t s5 6 ?0 5 1 o c recommended operating conditions (4) l o b m y sr e t e m a r a p. n i m. x a ms t i n u v c c e g a t l o v y l p p u s0 . 36 . 3 v v h i e g a t l o v t u p n i l e v e l h g i h0 . 2 v l i e g a t l o v t u p n i l e v e l w o l8 . 0 v i e g a t l o v t u p n i0 . 0v c c t a e r u t a r e p m e t r i a - e e r f g n i t a r e p o00 7c o i h o t n e r r u c t u p t u o l e v e l h g i h2 1 ? a m i l o t n e r r u c t u p t u o l e v e l w o l2 1 absolute maximum ratings (over operating free-air temperature range, unless otherwise noted) ? ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rati ngs only and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operatin g conditions? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect reliability. notes: 1. the input and output negative-voltage ratings may be exceeded if the input and output clam p-current ratings are observed. 2. this value is limited to 4.6v maximum. 3. maximum package power dissipation is calculated using a junction temperature of 150c and a board trace length of 750 mils. note 4. unused inputs must be held high or low to prevent them from floating.
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2516 phase-locked loop clock driver with 16 clock outputs 4 ps8440c 07/24/01 l o b m y sn o i t i d n o c t s e tv c c . n i m. p y t. x a ms t i n u v k i e g a t l o v p m a l c t u p n i ,a m 8 1 ? t a t n e r r u c t u p n iv 39 7 . 0 ?2 . 1 ? v v h o i h o =? a 0 0 1. x a m o t . n i mv c c 2 . 0 ?9 9 . 2 i h o =? a m 2 1 v 3 1 . 26 6 . 2 i h o =? a m 64 . 23 8 . 2 v l o i l o a 0 0 1 =. x a m o t . n i m1 0 . 02 . 0 i l o a m 2 1 = v 3 3 . 08 . 0 i l o a m 6 =5 1 . 05 5 . 0 i i t n e r r u c t u p n i ,v = e g a t l o v t u p n i k c o l c c c d n g r o v 6 . 3 5 a i , t n e r r u c y l p p u s g o l a n a c c v = e g a t l o v t u p n i k c o l c c c d n g r o2 1a m c i v = e g a t l o v t u p n i c c d n g r o v 3 . 3 0 . 40 . 4 f p c o v = e g a t l o v t u p t u o c c d n g r o0 . 6 d i c c v @ t u p n i e n o c c , v 6 . 0 ? v @ s t u p n i r e h t o c c d n g r o v 6 . 3 o t v 3 . 30 . 50 0 5a electrical characteristics (over recommended operating free-air temperature range) function table g xk l c] 3 : 0 [ y xt u o _ b f lll l lhl h hll l hhh h note: x is from 1 to 4
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2516 phase-locked loop clock driver with 16 clock outputs 5 ps8440c 07/24/01 r e t e m a r a p m o r f ) t u p n i ( o t ) t u p t u o ( v c c v 5 6 1 . 0 v 3 . 3 =v c c v 3 . 0 v 3 . 3 = s t i n u . n i m. p y t. x a m. n i m. p y t. x a m t e s a h p r o r r en i k l c - z h m 0 0 1 =n i b f - 0 5 1 ?0 7 1 + s p t ) o ( k s ) 2 ( t u o b f r o y y n a t u o b f r o y y n a 0 0 2 r e t t i j ) k p - k p ( ) z h m 6 6 > n i k l c ( f0 0 1 ?0 0 1 e l c y c y t u d n i k l c ( f ) z h m 6 65 45 5 % ) z h m 6 6 > n i k l c ( f5 45 5 t r z h m 0 5 1 o t 0 5 = n i k l c % 0 8 o t % 0 2 m o r f 3 . 11 . 27 . 01 . 2 s n t f 7 . 15 . 22 . 15 . 2 switching characteristics (over recommended ranges of supply voltage and operating free-air temperature, c l = 22pf) (1,3) notes: 1. these parameters are not production tested. 2. the t sk(o) specification is only valid for equal loading of all outputs. 3. the specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. notes: 1. operating clock frequency indicates a range over which the pll must be able to lock, but in which it is not required to meet the other timing parameters (used for low-speed system debug). 2. application clock frequency indicates a range over which the pll must meet all of the timing parameters. 3. time required for the integrated pll circuit to obtain phase lock of its feedback signal to its reference signal. for phase l ock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at clk. until phase lock is obtained, the specificati ons for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. 4. frequency and loading condition should not exceed 0.85 watt power dissipation (package limitation). please refer to graph 1. timing requirements (over recommended ranges of supply voltage and operating free-air temperature) l o b m y sr e t e m a r a p. n i m. x a ms t i n u f p o k l c y c n e u q e r f k c o l c r o t a r e p o ) 1 ( 5 20 5 1 z h m t p p a k l c y c n e u q e r f k c o l c n o i t a c i l p p a ) 4 , 2 ( 63 3 1 t n o i t a z i l i l b a t s p u r e w o p r e t f a e m i t n o i t a z i l i b a t s ) 3 ( ?1s m d i y c e l c y c y t u d k c o l c t u p n i0 40 6% 0 i cc (ma) clock frequency (mhz) 0 50 load = 22pf load = 10pf 100 150 200 250 300 350 50 100 150 graph 1. dynamic current vs. clock frequency (v cc = 3.6v, t a = 25c)
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2516 phase-locked loop clock driver with 16 clock outputs 6 ps8440c 07/24/01 parameter measurement information load circuit from output under test 22pf 500 w 50% v cc 50% v cc 3v 0v 50% v cc v oh v ol input output t pd t r t f 80% 20% 80% 20% voltage waveforms propagation delay times notes: 1. c l includes probe and jig capacitance. 2. all input pulses are supplied by generators having the following characteristics: clkin 100mhz, z o = 50 ohms, t r 1.2ns, t f 1.2ns. 3. the outputs are measured one at a time with one transition per measurement. clkin fbin fbout any y t phase error t sk(o) any y any y t sk(o) phase error and skew calculations
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2516 phase-locked loop clock driver with 16 clock outputs 7 ps8440c 07/24/01 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com .236 .244 .488 .496 .002 .006 seating plane .007 .010 .0197 bsc .004 .008 .319 1 48 12.4 12.6 6.0 6.2 0.50 0.17 0.27 8.1 0.05 0.15 0.09 0.20 x.xx x.xx denotes dimensions in millimeters .018 .030 0.45 0.75 .047 1.20 max bsc ordering information r e b m u n t r a pn / p g n i r e d r oe g a k c a p 6 1 5 2 c 6 i pa 6 1 5 2 c 6 i pp o s s t n i p - 8 4 48-pin thin shrink small-outlinepackage (a)
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